The present invention relates generally to optimization and, more specifically, to optimizing critical timing paths in integrated circuits.
Organizing circuits on a substrate of a semiconductor is a task that can achieve efficiencies in overall circuit speed when electronic design automation instructions are processed on a data processing system to reduce delays in circuit operation. The chief source of delay within a Very Large Scale Integrated (VLSI) circuit design is the time delay associated with signals traveling from one component to another. Time delay is a value determined for a wire based on the wire's resistance and capacitance in relation to the substrate to which it is coupled. For a given substrate and a given wire width, time delay is proportional to the length of the wire. Time delay can be a term that applies to a path that interconnects multiple components in a path. Time delay can be a term applied to plurality of paths that make up a circuit design.
A path is a geometric description of the interconnect between a set of pins or endpoints of one or more nets. A net is a subset of components in an integrated circuit design as well as the interconnection of the pins of the subset of components. Each path is associated with a path delay or timing delay. The path may pass through a net associated with a first component, and a net of a second component. The path can be a 2-pin net. Thus, the path may link two or more components together by including at least one endpoint or pin of each component. A pin is an input or an output wire to a component. A netlist describes all the components in a design, and describes how these components or pins on the components are interconnected. The netlist may be described in a text file that corresponds to the component. The netlist may be a derivative, through additional processing, of a file format that may be as described by Verilog, VHSIC Hardware Design Language (VHDL), among other high-level design languages. Verilog is a trademark of Cadence Design Systems.
In some cases, the signal needs to traverse a particular path in a time that is less than one clock period of the clock driving the integrated circuit. During a design phase it may be discovered that some paths cannot be traversed in such a time period. Such a path may be referred to as “critical timing path” herein. In such a case, if it is determined during design review for an integrated circuit that a critical timing path exceeds the clock period, many different approaches such as, for example, reducing the number of active or passive elements in the path or breaking a long path into two or more paths by the introduction of an intermediate stopping point may be applied to reduce the traversal time to below the limit.